With increased considerations of cost and reliability, there is a continuous demand for semiconductor devices with higher levels of integration, i.e., higher packing densities of transistors and other devices. In order to increase levels of integration, FinFET (fin Field Effect Transistor) devices are becoming very popular in semiconductor integrated circuits and other semiconductor devices in various applications. FinFET devices are transistors that utilize a semiconductor fin that extends above the substrate surface, as a channel region for transistors. The channel region has an increased area with respect to transistors with planar channels. In many cases, drive to reduce feature proportions and sizes results in changes in operational characteristics and cannot be made across the board, however.
The demand for higher levels of integration includes a push to reduce transistor channel length. Transistor channel lengths are limited to a certain level of reduction, however. If the channel length is reduced to be shorter than an operational limit, undesirable results such as short channel effects and punch through may occur. Anti-punch through layers are utilized under fins of FinFET transistors to reduce sub-threshold source-to-drain leakage and Drain-Induced Barrier Lowering (DIBL). Anti-punch through (APT) layers are formed by ion implantation through the fin and it is difficult and challenging to control the location of the APT layer with respect to the fin. Random dopant fluctuation of the APT layer can result when the ion implantation operation is carried out through the fin and this random dopant fluctuation results in mismatches between the fins. The performance of the FinFET transistors is also closely related to the location of the APT with respect to the fin. If the APT is formed in the substrate too deep beneath the fin, an undesirable short channel effect is created. The implantation through the fin also destroys the fin itself. When the APT layer is not formed deep enough into the substrate, the dopant impurities of the APT layer occupy the lower portion of the fin especially after the high heat treatments used in semiconductor manufacturing. These high heat treatments cause back-diffusion from the APT layer into the fin.
It would therefore be desirable to produce FinFET devices that include fins that have uniform characteristics throughout the device, are undamaged and include appropriately positioned APT layers that are not subject to diffusion into the fins.